The Circuit Episode 38: The Future of Transistor Design and Advanced Packaging
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Oct 16, 2023 In this engaging discussion, Huiming Bu, who manages the global semiconductor R&D agenda at IBM Research, shares insights into the future of transistor design. He highlights the exciting shift from FinFET to nanosheet architectures and explores advanced techniques like vertical transport FET and stacked transistors. The conversation also addresses the need for new innovations in 3D chiplet design and the role of major foundries like TSMC and Intel. Finally, Huiming emphasizes the collaborative efforts required to tackle the challenges in meeting the growing demand for computational power.
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3D Scaling
- Transistor scaling has been dominated by lateral scaling (X and Y directions).
- A new horizon is 3D scaling (Z direction), which hasn't been explored for logic applications.
3D Chip Technology Examples
- Intel's PowerVia technology uses the backside of a wafer for power distribution, like a basement in a building.
- AMD's MI300X chip achieved over 100 billion transistors using a chiplet architecture.
Chip Design Options
- Chip designers have more options than ever before, with advancements in transistor design and chiplet packaging.
- This creates a highly competitive environment in both foundry and chip design.