The Circuit

Mark Wade, Ayar Labs co-founder and CEO, joins Jesse Leiter, the company’s capital strategy leader, to explore silicon photonics and optical interconnects for AI data centers. They discuss electrical bandwidth bottlenecks, co-packaged optics, the manufacturing complexity behind photonic systems, TSMC and ecosystem partnerships, digital twins, standards, strategic funding, and the road toward commercialization and an IPO.

Tom Boger, Apple’s Mac and iPad marketing leader; Kaiann Drance, an iPhone and Apple Watch marketing executive; and Sri Santhanam, head of Silicon Engineering, discuss Apple’s latest chips. They explore 2-nanometer design, advanced packaging, thermal management, dual neural engines, unified memory, on-device AI, and hardware-level privacy protections.

Atlas, a new AI knowledge agent, kicks off a discussion of Broadcom’s surging custom ASIC business and why hyperscaler chip programs are becoming tougher to model. The conversation explores supply bottlenecks peaking in 2027, possible oversupply and margin pressure in 2028, Nvidia’s Hugging Face acquisition, and why open and closed AI models will coexist.

NVIDIA’s supply constraints, rising component costs, and neocloud financing commitments take center stage. Marvell’s XPU-attach strategy raises questions about custom silicon and future revenue. Hot Chips reveals a fiercely unsettled inference landscape, from competing accelerator designs and software hurdles to custom HBM base dies and Waymo’s workload-specific silicon.

They unpack ADI’s surge in data center revenue and the rising role of analog content per gigawatt. They contrast AI hype with real bioinformatics developments and local pushback on massive data center builds. They analyze custom ASIC wins like Marvell’s expansion with Google and explore how chipmakers are using equity, warrants, and SPVs to fund data center capacity.

They dig into divergent optical supplier results and the manufacturing headaches of moving to six-inch indium phosphide wafers. They explain competing optics approaches like Linear Pluggable, Near-Packaged, and Co-Packaged optics and why rack-to-rack wins for now. They unpack Cisco's Silicon One comeback and clever use of an LLM for security audits. They debate vendor-backed data center financing and whether compute is a durable investable asset.

They break down AMD’s steady quarter, wafer limits, CapEx questions and why investors felt mixed. Reporting from a packed Future of Memory Summit, they highlight the surge in memory momentum and CXL demos. They explain rack-scale AI driving DDR4 reuse and the TCO case for CXL. They debate memory pricing durability and call out companies poised to benefit from timing and CXL supply-chain wins.

They trace mobile market weakness and probe whether it is demand-driven or caused by supply constraints at Apple, Qualcomm, ARM, and MediaTek. They unpack how surging AI compute is eating foundry and memory capacity and creating winners and losers in the supply chain. They examine hyperscaler CapEx shifts, behind-the-meter power moves, severe electrical labor shortages, and rising debt financing for data center builds.

They break down AMD’s Advancing AI announcements, including Helios rack-scale design and inference partnerships. They analyze Intel’s strong quarter and cautious CapEx messaging. They explore rising semiconductor equipment demand as fabs ramp spending. They note Texas Instruments’ recovery and growing power semiconductor needs tied to AI infrastructure.

Discussion of TSMC's raised CapEx and what it signals for foundry capacity and advanced packaging. Debate over shifts from Moore's Law to AI/HPC-driven wafer and equipment demand. Review of ASML's capacity, high-NA EUV implications and supplier constraints. Examination of AIR's burn-in testing role and broader test ecosystem. Exploration of AI-driven market rotation, rack economics and adoption timing.