Joren Vaes

In this engaging discussion, Joren Vaes, a design engineer at SOFICS with expertise in high-speed analog and wireline PHY/IP development, dives into the complexities of modern IC design. He emphasizes the crucial role of simulation in handling intricate parasitics across many metal layers and explains the challenges posed by massive DRC rules. Joren also shares insights into cutting-edge technologies like FinFETs and CFETs, the impact of electromigration on device reliability, and how to navigate the transition from digital to analog processes at high frequencies.