The Amp Hour Electronics Podcast #706 – Leading Edge Analog with Joren Vaes
Oct 18, 2025
In this engaging discussion, Joren Vaes, a design engineer at SOFICS with expertise in high-speed analog and wireline PHY/IP development, dives into the complexities of modern IC design. He emphasizes the crucial role of simulation in handling intricate parasitics across many metal layers and explains the challenges posed by massive DRC rules. Joren also shares insights into cutting-edge technologies like FinFETs and CFETs, the impact of electromigration on device reliability, and how to navigate the transition from digital to analog processes at high frequencies.
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Modeling Is The Heart Of Analog Success
- Analog IC design relies on extremely detailed transistor models and heavy simulation to predict real silicon behavior.
- Engineers can reach a few percent accuracy if they model parasitics and device details thoroughly.
From Colored Pencils To Transistor Masks
- Joren recalled being forced to draw transistor masks by hand, down to implants and oxide regions.
- He still often draws transistor rectangles and process-level features during layout.
The Rulebook Grows With Each Node
- Advanced process nodes come with massive rulebooks that grow each generation.
- These rules tightly constrain layout choices to ensure manufacturability and predictable physics.
