Andreas Olofsson, Co-founder of ZeroASIC, discusses accessible ASICs and open-source impact on silicon designs. He explains the concept of chiplets and the basis of his company ZeroASIC. They offer a drag and drop interface for customers to create custom ASICs. Andreas also talks about the advantages of their assembly process and the potential of ZeroASIC in aerospace and defense. The podcast covers topics like ball grid arrays, system-on-module, AWS servers, ML chiplets, remote work in hardware development, and circuit design with Lego-like bricks.
Zero ASIC aims to reduce barriers to silicon design by developing a standard for chiplets that can be combined to create customized chips.
Hardware community faces challenges with contributions and standards compared to software community, requiring ideal conditions for external contributions.
Zero ASIC builds their own chiplets instead of relying on off-the-shelf options, ensuring compatibility and addressing the lack of plug-and-play capabilities in the market.
Deep dives
Zero ASIC's Journey: From Start to Present
Zero ASIC is a company that aims to reduce the barrier to silicon design. They started by building a standard for chiplets, which are specialized IP blocks that can be combined to create customized chips. Their target market is people who need specialized performance but don't have infinite money. They have focused on industries like aerospace and defense, where size, weight, and power constraints are critical. Zero ASIC has developed chiplets for CPU, FPGA, and machine learning accelerators. They are working on creating a full-stack chiplet interface standard to foster an ecosystem and drive adoption. The goal is to make chiplets plug-and-play, similar to USB or PCIe. While building a standard is challenging, Zero ASIC is determined to bootstrap an ecosystem and make specialized silicon design more accessible.
Challenges in Hardware Community and Contributions
The hardware community faces challenges when it comes to contributions and standards compared to the software community. Hardware standards require significant time and effort, given the larger size of the community. External contributions are rare and often require ideal conditions, such as a skilled contributor with niche expertise and ample time to spare. Companies receiving contributions must appreciate the rarity of such contributions and cannot fully rely on them. Zero ASIC's experience reflects these challenges, where external contributors are a valuable addition when the environment aligns perfectly. The company appreciates the hardware community's support and engagement, as seen in events like Latch-Up, which foster a friendly and welcoming environment.
Zero ASIC's Approach to Chiplet Design and Custom Silicon
Zero ASIC's approach to chiplet design involves building their own chiplets rather than relying on off-the-shelf options. This decision stems from the need for specialized chiplets that have specific interfaces for seamless communication. By building chiplets themselves, Zero ASIC ensures compatibility and addresses the lack of plug-and-play capabilities in the market. They bootstrap an ecosystem by creating a chiplet standard that defines pinouts, electrical interfaces, and abstraction layers. Zero ASIC envisions a marketplace where other vendors can contribute chiplets, driving broader adoption. Their current focus on chiplets includes CPU, FPGA, and machine learning accelerators. Zero ASIC's aim is to provide performance-centric, cost-constrained markets with the ability to customize silicon and overcome barriers to entry.
The Benefits of Using Chiplets in Hardware Design
Chiplets offer advantages in terms of scalability and cost-effectiveness in hardware design. By using pre-designed chiplets from IP vendors, companies can avoid the time-consuming and costly process of designing their own IP, IO libraries, and other components. This outsourcing of development to IP vendors allows for faster and more efficient design processes. While some may question the need for lower-level design when using chiplets, standardization and efficiency play crucial roles in favor of using someone else's work. The optimal pricing of chiplets further encourages their adoption in the industry, striking a balance between affordability and incentivizing buying them rather than building from scratch.
Understanding the Concept of Chiplets and its Definition
The concept of chiplets involves using separate dies with specialized IO interfaces that are designed for in-package integration. Chiplets can vary in size and complexity, ranging from small silicon dies to large SOCs in a package. A chiplet typically consists of a die with a short-range IO interface that enables integration within a package. While chiplets are often soldered onto an organic substrate or a silicon passive interposer, their connectivity and configuration can differ based on specific design requirements. The key advantage of chiplets lies in providing modularity similar to software, allowing for easier reuse, customization, and overall flexibility in hardware design.
