Using Soft Terminal Caps to Reduce Out of Plane Vibration

In the end we were able to reduce CTE over 50% and meet our performance by 3x over our initial version. Solving density at every level is the cornerstone of actually achieving our system performance. Because our xy plane is used for high bandwidth communication everything else must be stacked vertically. Now in this case the failure is due to losing clock output from our oscillators. And after an extensive debug we found that the root cause was due to vibrations on the module from piezoelectric effects on nearby capacitors.

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