For decades, semiconductor fabs tolerated—and even expected—bad yields. Less than 50%, sometimes as low as 10%. Credible die yield data is rare, but here’s a market analysis from the late 1980s for the US Trade Representative during the US-Japan semiconductor dispute. It implies that when American and Japanese firms began 16K DRAM in 1978, yields were about 2%. Laughably low, but expected. And they stayed low. By 1984, US 16K DRAM yield hit 36%. Japan: 48%—better, still bad. Six years later! Now look at TSMC’s N5/N4 node, about 4–5 years old. Trade secrets, but N4 yields are around 80%. What’s going on? 6-micron process vs. 4-nanometer. The latter is far harder. Yet we’re hitting 80–90% yields. Is it a conspiracy? No—the fabs opened their third eyes. With new tools, they began inspecting and improving. In this video: how automated inspection tools revolutionized chip fabrication.
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