Mark Himelstein, CTO of RISC-V joins us to discuss the latest developments with the RISC-V instruction set architecture (ISA) and its growing community and footprint. Topics include HPC type use cases from sensor to supercomputer, achieving customization without loss of compatibility, AI and its impact on chips and systems, and the question on everyone’s mind: when do we see RISC-V in servers and supercomputers!
You may also be interested in Shahin’s conversation with Mark in August 2020 and see how things have evolved.
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