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Hardware for ZKPs & VDFs with Supranational

Zero Knowledge

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The Challenges of Scaling a CPU Implementation

With the VDF, you want to make it go as low latency as possible. To repeat a squaring with low latency, we initially built an FPGA implementation. So a CPU implementation would be about 1100 nanoseconds per squaring. For FPGA, we got it down to about 65 nanosecondS per squaring so quite a bit faster.

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